Bit line decoding scheme and circuit for dual bit memory with a dual bit selection
US6643172B2 · kind B2 · utility
7Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 8, 2002 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In the present invention a bit line decoder scheme is described that connects data and voltage to a plurality of bit lines of a dual bit flash memory array. The bit lines are connected to a plurality of intermediate data lines by a first decoder unit and the intermediate data lines are connected to a plurality of data lines of the sense amplifiers by a second decoder unit. In one embodiment the voltage is connected to a selected bit line through a separate decoder unit and in a second embodiment the voltage is connected through the decoder unit connected to the intermediate data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.