Method for improving read margin in a flash memory device
US6643177B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2003 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Jan 21, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array. The dynamic reference array and an associated core memory cell array are programmed using two different programming processes to produce different Vt distributions for the dynamic reference array and the core memory cell array. The dynamic reference array is programmed using a finer program pulse to achieve a smaller distribution width, thus enhancing the read margin for the memory cell array. The finer pulse may be of shorter duration or of smaller amplitude. The finer programming process may be applied to one or more threshold voltage distributions (states) in the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.