Transceiver with latency alignment circuitry
US6643752B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1999 |
| Grant date | Nov 4, 2003 |
| Priority date | — |
| Expiry date | Dec 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transceiver system is described. A secondary memory module is coupled to a primary channel for receiving data and signals from a controller. The secondary memory module comprises a memory and a secondary channel for transmitting the data and control signals to the memory. The secondary memory module further comprises a transceiver coupled to the primary channel and the secondary channel. The transceiver is designed to electrically isolate the secondary channel from the primary channel. The transceiver is a low latency repeater to permit the data and the control signals from the controller to reach the memory, such that a latency of a data request from the controller is independent of a distance of the transceiver from the controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.