Method to determine a complete etch in integrated devices
US6645781B1 · kind B1 · utility
5Cited by
13References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2002 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Apr 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an integrated device, an etch is performed in an intermediate layer to form a via. The via is inspected using a scanning electron microscopy. The scanning electron microscopy detects a level of brightness associated with the via and a background shade. Whether the etch reached an etch-stop layer is determined by comparing the level of brightness associated with the via to the background shade.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.