Multi-layered polysilicon process
US6645840B2 · kind B2 · utility
3Cited by
14References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Sep 28, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28123
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a notched MOS gate structure is described. A multi-layer gate structure is formed (150) where the top layer (140) oxidizes at a faster rate compared to the bottom layer (130). This results in the formation of a notch (165) in the gate structure after thermal oxidation processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.