Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6646322B2 · kind B2 · utility
63Cited by
13References
19Claims
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Key dates
| Filing date | Jul 16, 2001 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Jul 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/637
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.