Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies
US6646928B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2003 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Jan 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/3042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate. The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.