Latent defect classification system
US6647348B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 2001 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Dec 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2894
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for identifying an integrated circuit having a latent defect. Test data corresponding to a set of integrated circuits is obtained, where the set of integrated circuits was processed on a single substrate. A subject integrated circuit is selected for analysis from within the set. A subset of integrated circuits is identified from within the set, where the subset includes integrated circuits that were located in close proximity on the substrate to the subject integrated circuit. The test data for the subset is analyzed to determine a defect parameter for the subset. The defect parameter for the subset is compared to a threshold. The subject integrated circuit is classified as having a latent defect when the defect parameter for the subset violates the threshold, and the subject integrated circuit is classified as not having a latent defect when the defect parameter for the subset does not violate the threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.