Apparatus and method for shift register rate control of microprocessor instruction prefetches
US6647487B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Nov 11, 2003 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and methods for optimizing prefetch performance. Logical ones are shifted into the bits of a shift register from the left for each instruction address prefetched. As instruction addresses are fetched by the processor, logical zeros are shifted into the bit positions of the shift register from the right. Once initiated, prefetching continues until a logical one is stored in the nth-bit of the shift register. Detection of this logical one in the n-th bit causes prefetching to cease until a prefetched instruction address is removed from the prefetched instruction address register and a logical zero is shifted back into the n-th bit of the shift register. Thus, autonomous prefetch agents are prevented from prefetching too far ahead of the current instruction pointer resulting in wasted memory bandwidth and the replacement of useful instruction in the instruction cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.