Wafer coating and singulation method
US6649445B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Sep 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for providing an underfill material on an integrated circuit chip at the wafer level. The wafer (10) typically contains one or more integrated circuit chips (12), and each integrated circuit chip typically has a plurality of solder bumps (34) on its active surface. The wafer is first diced (22) on the active surface side to form channels (38) that will ultimately define the edges (39) of each individual integrated circuit chip, the dicing being of such a depth that it only cuts part-way through the wafer. The front side (36) of the wafer is then coated (24) with an underfill material (40). Generally, a portion (45) of each solder bump remains uncoated, but in certain cases the bumps can be completely covered. The back side of the wafer is then lapped, ground, polished or otherwise treated (26) so as to remove material down to the level of the previously diced channels. This reduction in the thickness of the wafer causes the original diced channels to now extend completely from the front side to the back side of the wafer. The wafer is then singulated (28) by cutting the underfill material (92) that was deposited in the channels during the coating step, so that the integrat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.