Method for ultra-thin gate oxide growth
US6649535B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Feb 12, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02312
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an ultra-thin (between about 15 to 20 Angstroms), silicon dioxide gate insulator layer, featuring a process sequence which widens the process window of the thermal oxidation procedure, and improves the quality of the ultra-thin silicon dioxide gate insulator layer, has been developed. After a series of wet clean procedures applied to a semiconductor substrate, a high temperature anneal procedure is performed in an inert ambient. The high temperature anneal removes organic, as well as inorganic material not removed during the wet clean procedures, and also removes native oxide formed during these same wet clean procedures. The removal of these materials allow the use of longer thermal oxidation times still resulting in silicon dioxide thickness equal to counterparts formed using shorter oxidation times, which were not subjected to the pre-oxidation high temperature anneal procedure. In addition to the widening of the process window, or the use of extended oxidation times, allowed the use of higher oxidation temperatures, resulting in silicon dioxide gate insulator layers exhibiting higher dielectric quality than counterparts formed using lower oxidation temperat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.