Selective C4 connection in IC packaging
US6650016B1 · kind B1 · utility
11Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Oct 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10674
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.