Method and apparatus to enhance testability of logic coupled to IO buffers
US6650136B2 · kind B2 · utility
1Cited by
4References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 16, 2001 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318591
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.