Semiconductor memory device
US6650582B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2002 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Aug 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For a memory array, a main data bus commonly used for first and second data bit widths, and a main data bus used only for the second data bit width are disposed. According to a data bit width, connection between memory blocks and main data lines is switched. The main data buses are connected to write/read circuits, and expanding/compressing operation on data bits is performed by an expansion/compression circuit in a unit of a predetermined number of bits. Thus, with the same configuration irrespective of data bit width, compression of data bits in the multi-bit test can be performed to output the compression result to the same data terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.