Phase lock loop and transconductance circuit for clock recovery
US6650720B1 · kind B1 · utility
12Cited by
13References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 1998 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Dec 22, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high speed data communication system includes a receiver to recover data and clock signals from communicated data. The receiver circuit has a dual phase lock loop (PLL) circuit. A fine loop of the PLL includes a phase detector providing a differential analog voltage output. Transconductance circuitry converts the differential analog voltage output to a low current analog output. The transconductance circuitry has a high impedance output, a small transconductance value and can provide variable gain control. A coarse loop of the PLL allows for frequency acquisition of an internal oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.