System and method for testing on-chip modules and the interconnections between on-chip modules
US6651198B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Jan 7, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An improved system for testing the operation of component modules and the interconnections therebetween of an integrated circuit (10) formed on a semiconductor chip is provided which consists of several component modules, each with an associated input scan cell (76) and output scan cell (102) when necessary. A component module may have both an input scan cell (76) and an output scan cell (102) unless the input or output of that component module occurs on the boundary of the integrated circuit (10). Each output scan cell (102) has a mode select signal (122) which indicates either input test mode or output test mode. The improved scan test system uses two process steps to verify the operational integrity of the entire integrated circuit (10). During the first step of the scan test, non-adjacent component modules have their mode select signals set to output test mode, and component modules existing between the non-adjacent component modules have their mode select signals set to input test mode. During the second step of the scan test, all mode select signals are reset to the opposite setting. After the second step of the scan test, the operational integrity of all component modules an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.