Scalable, partitioning integrated circuit layout system
US6651235B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2001 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Oct 30, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) layout system initially modifies a netlist describing an IC as a hierarchy of circuit modules to combine clusters of cells forming selected modules so that they form a smaller number of larger cells. This reduces the number of cells forming the IC, thereby reducing the time the system needs to generate an IC layout. The system then generates a trial layout of the IC described by the modified netlist. Based on the shape and position of the area each module occupies in the trial layout, the system estimates the shape and position of a substrate area each module would require in a layout where module areas did not overlap. The system then divides the IC design into several partitions, each including separate set of the modules forming the IC, and creates a partition plan allocating substrate space to each partition based on the estimated space requirement of each module assigned to that partition. The system also creates a timing budget allocating signal path timing constraints among the partitions based on an timing analysis of signal paths delays in the trial layout. Thereafter the system independently lays out each IC partition so that it satisfies that p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.