System and method for insertion of prefetch instructions by a compiler
US6651245B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2000 |
| Grant date | Nov 18, 2003 |
| Priority date | — |
| Expiry date | Feb 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method and device for placing prefetch instruction in a low-level or assembly code instruction stream. It involves the use of a new concept called a martyr memory operation. When inserting prefetch instructions in a code stream, some instructions will still miss the cache because in some circumstances a prefetch cannot be added at all, or cannot be added early enough to allow the needed reference to be in cache before being referenced by an executing instruction. A subset of these instructions are identified using a new method and designated as martyr memory operations. Once identified, other memory operations that would also have been cache misses can “hide” behind the martyr memory operation and complete their prefetches while the processor, of necessity, waits for the martyr memory operation instruction to complete. This will increase the number of cache hits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.