Measured via-hole etching
US6653214B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jan 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit substrate via-hole fabrication arrangement providing for accurate determination of via-hole size and via-hole registration through use of a calibrated pattern formed into the integrated circuit substrate during portions of the normal circuit fabrication process. Initiation of the via-hole and fabrication of the calibrated pattern from one surface, such as the front side, of the integrated circuit wafer and completion of the via-hole from the opposite surface of the wafer are contemplated. The calibrated pattern may be one of several possible physical configurations and of selected dimensions usable with the process, materials and circuitry of the device being fabricated. Use of the invention in fabricating ground conductor-connected via conductors for gigahertz radio frequency-capable integrated circuits of the monolithic or mixed hybrid with monolithic type and having a ground plane element is contemplated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.