Semiconductor integrated circuit, method and program for designing the semiconductor integrated circuit
US6653868B2 · kind B2 · utility
25Cited by
2References
11Claims
0Family size
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Key dates
| Filing date | Jun 18, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Jun 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit that is well-balanced between increased operating speed and decreased power consumption caused by a leakage current. The gate cells of the circuit comprised of low threshold voltage MOSs are used for logic gates provided with three or more inputs, and gate cells comprised of high threshold voltage MOSs are generally used for logic gates provided with one or two inputs, sometimes on a case-by-case basis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.