Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
US6653876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Apr 23, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated by dividing the first frequency of the first clock signal by two, such that the second frequency is half of the first frequency and a duty cycle of the second clock signal is 50%. Also, a set of phase-delayed clock signals is generated in response to the second clock signal such that the set of phase-delayed clock signals are delayed in phase with respect to the second clock signal. Further, the set of phase-delayed clock signals is combined to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of the third clock signal is 50%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.