Well bias control circuit
US6653890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2002 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Oct 31, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor integrated circuit device having a control mechanism 11 for compensating not only circuit operational speed but also variations in leakage current, which includes: a main circuit 10 constructed by a CMOS; a delay monitor 21 for simulating a critical path of the main circuit 10 constructed by a CMOS and monitoring a delay of the path; a PN Vt balance compensation circuit 23 for detecting a threshold voltage difference between a PMOS transistor and an NMOS transistor; and a well bias generating circuit 25 for receiving outputs of the delay monitor 21 and the PN Vt balance compensation circuit 23 and applying a well bias to the delay monitor 21 and the main circuit 10 so as to compensate the operation speed of the delay monitor 21 to a desired speed and reduce a threshold voltage difference between the PMOS and NMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.