System for rejecting and reissuing instructions after a variable delay time period
US6654876B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1999 |
| Grant date | Nov 25, 2003 |
| Priority date | — |
| Expiry date | Nov 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, processor, and data processing system implementing a delayed reject mechanism are disclosed. The processor includes an issue unit suitable for issuing an instruction in a first cycle and a load store unit (LSU). The LSU includes an extend reject calculator circuit configured to receive a set of completion information signals and generate a delay value based thereon. The LSU is adapted to determine whether to reject the instruction in a determination cycle. The number of cycles between the first cycle and the determination cycle is a function of the delay value such that reject timing is variable with respect to the first cycle. In one embodiment, the processor is further configured to reissue the instruction after the determination cycle if the instruction was rejected in the determination cycle. The delay value is conveyed via a 2-bit bus in one embodiment. The 2 bit bus permits delaying the determination cycle from 0 to 3 cycles after a finish cycle. In one embodiment, the number of cycles between the first cycle and the determination cycle includes the number of cycles required to travel a pipeline of the microprocessor plus the number of cycles indicated by the delay …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.