Method of fabricating a ferroelectric stacked memory cell

US6656801B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Chiara Corvasce · Bergdietikon, CH
• Raffaele Zambrano · Catania, IT

Key dates

• Filing date: Jul 23, 2001
• Grant date: Dec 2, 2003
• Expiry date: Jul 23, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/485

Abstract

The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material. In this way, the manufacturing process is not critical and the size of the cells is minimal.