Manufacturing process for semiconductor wafer comprising surface grinding and planarization or polishing
US6656818B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 2001 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | May 16, 2021 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB24B7/228
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
Provided is a manufacturing process for a semiconductor wafer according to which semiconductor wafers each with higher flatness can be manufactured with good efficiency from a wafer work having passed through a surface grinding step by enabling restriction of reduction in flatness in the vicinity of the center and in the outer peripheral edge portion of a surface ground wafer at the lowest level possible, and correction of the reduction in flatness of both portions with ease to planarize in a planarization or polishing step. When a semiconductor wafer fixed on a chuck table is surface ground using a cup shaped grinding wheel, the semiconductor wafer is ground toward the center thereof such that the grinding wheel cuts into the semiconductor wafer at the outer peripheral edge thereof and moves away from the semiconductor wafer at the central portion thereof and the ground semiconductor wafer is planarized according to a PACE method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.