Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch
US6656824B1 · kind B1 · utility
20Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for fabricating low-resistance, sub-0.1 &mgr;m channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate such MOSFETs. The chemical oxide removal may be performed in a vapor containing HF and NH3 or a plasma containing HF and NH3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.