Electrical performance enhanced wafer level chip scale package with ground
US6656827B1 · kind B1 · utility
91Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Oct 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method including providing a first substrate having a first bond pad and a second bond pad; forming a subassembly comprising securing a second substrate to the first substrate with a ground layer interposed between the first substrate and the second substrate; forming a first trench in the subassembly through the first substrate so that the trench is defined at least in part by a side wall of the first substrate and through at least a portion of the ground layer; and forming a first electrically conductive layer overlying the first bond pad, the side wall of the first substrate and overlying a portion of the ground layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.