Jones Wang
9Patents
6h-index
9Co-inventors
52Inventor score
Filing activity: Jul 26, 2001 → Dec 23, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6656827B1 | Electrical performance enhanced wafer level chip scale package with ground | Electricity | 91 | Expired |
| US6939789B2 | Method of wafer level chip scale packaging | Electricity | 58 | Expired |
| US6607942B1 | Method of fabricating as grooved heat spreader for stress reduction in an IC package | Electricity | 37 | Expired |
| US9754849B2 | Organic-inorganic hybrid structure for integrated circuit packages | Electricity | 34 | Active |
| US6960518B1 | Buildup substrate pad pre-solder bump manufacturing | Electricity | 7 | Expired |
| US7015066B2 | Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly | Emerging Cross-Sectional Technologies | 7 | Expired |
| US6638837B1 | Method for protecting the front side of semiconductor wafers | Electricity | 5 | Expired |
| US6884662B1 | Enhanced adhesion strength between mold resin and polyimide | Electricity | 1 | Expired |
| US7390697B2 | Enhanced adhesion strength between mold resin and polyimide | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.