Plasma treatment method for fabricating microelectronic fabrication having formed therein conductor layer with enhanced electrical properties
US6656832B1 · kind B1 · utility
20Cited by
2References
7Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 25, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Jul 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a microelectronic fabrication provides for forming a patterned conductor layer into a via defined by a pair of dielectric layers. Within the method, the via is plasma treated prior to forming therein the patterned conductor layer with at least one of: (1) an argon containing plasma with each of a radio frequency source power density and a radio frequency bias power density of less than about 300 watts; and (2) a hydrogen containing plasma with a radio frequency source power of greater than about 400 watts and a radio frequency bias power density of greater than about 100 watts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.