Electrical and physical design integration method and apparatus for providing interconnections on first level ceramic chip carrier packages
US6657130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2001 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Sep 20, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4916
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer ceramic semiconductor chip carrier is provided by a method of interconnecting ground, signal and power lines in a semiconductor chip carrier. The method involves forming a plurality of insulating layers with conductor lines comprising power and ground lines connected in parallel in a single plane formed in planes between the insulating layers. The parallel lines are directed in orthogonal directions in parallel between any two of the insulating layers with alternation successively between planes of X-directed lines and planes of Y-directed coplanar signal, power and ground lines. There are via connections formed between planes connecting a power line in one plane to another power line in another plane. Other via connections between planes connect a ground line in a first plane to another ground line in a second plane, and signal lines are formed in parallel between a ground line and a power line in a given plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.