ESD structure having an improved noise immunity in CMOS and BICMOS semiconductor devices

US6657241B1 · kind B1 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Mark Rouse · Snohomish, US
• Andrew J. Walker · Mountain View, US
• Brenor L. Brophy · San Jose, US
• Kenelm G. D. Murray · Chiddingfold, GB

Key dates

• Filing date: Apr 10, 1998
• Grant date: Dec 2, 2003
• Expiry date: May 13, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (Vss) and/or Vcc for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n+-type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n+ source subregions, or, (ii) a region that is generally annular in shape and surrounds the n+ source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.