Formation of an embedded capacitor plane using a thin dielectric
US6657849B1 · kind B1 · utility
58Cited by
18References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Aug 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09309
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A capacitor, which has a pair of conductive foils each having a dielectric layer on its surface, wherein the dielectric layers are attached to one another. In one process for its production, a capacitor is formed by applying a first dielectric layer onto a surface of a first conductive foil; applying a second dielectric layer onto a surface of a second conductive foil; and then attaching the first and second dielectric layers to one another. The resulting capacitor exhibits excellent void resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.