Memory sense amplifier
US6657909B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Jul 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory sense amplifier unit for amplifying a data signal read from a memory via bit lines (2, 3), having a precharge circuit (4) comprising PMOS transistors (5, 6) and serving for rapidly precharging the bit lines (2, 3) to a supply voltage potential (VDD) of the sense amplifier unit (1); a first amplifier stage (43) comprising feedback NMOS transistors (21, 22, 24, 26) and serving for voltage level shifting and for amplifying the data signal present on the bit lines (2, 3); and having a second amplifier stage (66) for amplifying further the signal output by the first amplifier stage (43), in which case the first amplifier stage (43) can be initialized to the supply voltage potential (VDD) and the second amplifier stage (43) can be initialized to ground potential (VSS).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.