Pipelined asynchronous processing
US6658550B2 · kind B2 · utility
25Cited by
11References
1Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 30, 2002 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | May 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0855
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.