Compilable address magnitude comparator for memory array self-testing
US6658610B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Nov 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1802
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory. As such, the BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. Thus, the BIST controller is able to test memory arrays without regard for their particular size.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.