System and method for silent data corruption prevention due to next instruction pointer corruption by soft errors
US6658621B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Oct 29, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for checking and correcting soft errors in a next instruction pointer is described. In one embodiment, a parity bit is generated for a next instruction pointer that is produced in a front end of a processor. The next instruction pointer and the parity bit are staged from the front end of the processor to a back end of the processor. Another next instruction pointer is generated in the back end of the processor when an instruction corresponding to the next instruction pointer generated in the front end executes. The next instruction pointer generated in the back end is also parity protected. The next instruction pointer generated in the front end is checked for a parity error. The next instruction pointer generated in the back end is also checked for the parity error. Finally, both next instruction pointers are compared to determine if both are equal. Based on whether the next instruction pointer generated in the front end has the parity error, whether the next instruction pointer generated in the back end has the parity error, and whether both next instruction pointers are equal, a control logic generates an exception or flushes a pipeline in the processor and f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.