Automated system-on-chip integrated circuit design verification system
US6658633B2 · kind B2 · utility
85Cited by
2References
24Claims
0Family size
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Key dates
| Filing date | Oct 3, 2001 |
| Grant date | Dec 2, 2003 |
| Priority date | — |
| Expiry date | Nov 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of verifying the design of an integrated circuit chip comprised of one or more cores, comprising: creating a project core catalog comprising driver description files and application description files for each core; creating a system definition file for the integrated circuit chip; inputting the driver description files, the application description files and the system definition files into a code generator, the code generator outputting a test operating system test code; and applying the test operating system test code to a software simulation of the integrated circuit chip to perform design verification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.