Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby
US6660564B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 25, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Feb 14, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/50
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate. Metal pads are then formed through the SOI substrate to the metal connectors within the cavity. Wire bond pads are thereby connected to the functional element without opening the cavity to the environment. Elect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.