Flip chip molded/exposed die process and package structure
US6660565B1 · kind B1 · utility
5Cited by
12References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Sep 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with the objectives of the invention a new method is provided to insert the underfill for flip-chip semiconductor devices. An IC chip is provided with solder bumps. The flip-chip is entered into an enclosed space, the heatsink forms the top of the enclosed space, the substrate forms the bottom of the enclosed space. The enclosed space is filled with a mold compound. This mold compound now surrounds the IC chip thereby including the area below the IC. The step of inserting the underfill as a separate processing step has thereby been eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.