BiLevel metallization for embedded back end of the line structures
US6660568B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 7, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Nov 7, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
MRAM cells are placed in the upper regions (BEOL) of an integrated circuit while simultaneously maintaining the dimensions needed for good MRAM performance and also for good operation of the logic circuit by setting the standard vertical dimension of the BEOL at the value that is suitable for logic circuits. In the areas where MRAM cells are to be placed, the (N+1)th level is etched separately. A standard etch is applied in logic areas and a deeper etch is applied in MRAM areas, so that the interlevel distance in the logic areas is the standard amount and the interlevel distance is MRAM areas is a lesser amount that is appropriate to accommodate the vertical dimensions of the material layers that go into the MRAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.