Method for fabricating metal gates in deep sub-micron devices
US6660577B2 · kind B2 · utility
5Cited by
6References
13Claims
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Key dates
| Filing date | Feb 23, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Apr 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating metal gates in deep sub-micron CMOS devices. The method blanket deposits a transition metal nitride layer on top of a gate dielectric layer for forming gate electrodes for both a PMOS and an NMOS device. After a cap layer is deposited on top of the gate electrode for PMOS, a rapid thermal annealing process is carried out to drive out nitrogen from the transition metal nitride on top of the NMOS. Gate electrodes having different work functions on top of the PMOS and NMOS are thus achieved simultaneously by the same fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.