Zero power memory cell with improved data retention

US6660579B1 · kind B1 · utility

Assignee

• Lattice Semiconductor Corporation · US

Inventors

• Chun Jiang · San Jose, US
• Sunil Mehta · Rumford, US
• Stewart Logie · Campbell, US

Key dates

• Filing date: Apr 24, 2002
• Grant date: Dec 9, 2003
• Expiry date: May 15, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method for forming a three transistor zero power memory cell including a p-channel sense transistor, an n-channel write transistor, and an n-channel sense transistor including: implanting a p-type impurity into a p-type substrate in which a n-channel high voltage transistor will be formed; implanting an n-type impurity into an n-type well in a p-type substrate in which a p-channel high voltage transistor will be formed; forming a mask to allow implants to occur to p-channel devices; performing a series of n-type dopant implants into the substrate where the p-channel transistors will be formed; growing a high voltage gate oxide; forming a mask to allow implants to occur to n-channel devices, said mask blocking implants to said n-channel sense transistor; and performing a series of p-type implants into the substrate where the n-channel devices will be formed. In addition, a memory cell which may include a first NMOS transistor having a source, drain and gate, and a first PMOS transistor is disclosed. The memory cell includes a first and second NMOS transistors, and a PMOS transistor, wherein the first NMOS transistor and first PMOS transistor each include a three implant channel re…