Chun Jiang
44Patents
11h-index
23Co-inventors
75Inventor score
Filing activity: Jun 23, 1993 → May 24, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6628961B1 | Device and a method for connecting a mobile phone handset to an external keyboard | Electricity | 93 | Expired |
| US6307541A | Method and system for inputting chinese-characters through virtual keyboards to data processor | Physics | 48 | Expired |
| US5587665A | Testing hot carrier induced degradation to fall and rise time of CMOS inverter circuits | Physics | 43 | Expired |
| US6440839B1 | Selective air gap insulation | Electricity | 30 | Expired |
| US6600188B1 | EEPROM with a neutralized doping at tunnel window edge | Electricity | 22 | Expired |
| US5925914A | Asymmetric S/D structure to improve transistor performance by reducing Miller capacitance | Electricity | 20 | Expired |
| US5637902A | N-well resistor as a ballast resistor for output MOSFET | Electricity | 17 | Expired |
| US6593632B1 | Interconnect methodology employing a low dielectric constant etch stop layer | Electricity | 14 | Expired |
| US5339270A | AC drain voltage charging source for PROM devices | Physics | 14 | Expired |
| US6069485A | C-V method to extract lateral channel doping profiles of MOSFETs | Electricity | 13 | Expired |
| US6166558A | Method for measuring gate length and drain/source gate overlap | Electricity | 11 | Expired |
| US6649514B1 | EEPROM device having improved data retention and process for fabricating the device | Electricity | 8 | Expired |
| US6137126A | Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer | Emerging Cross-Sectional Technologies | 8 | Expired |
| USD1047506S1 | Curtain mounting frame | General | 8 | Active |
| US6110219A | Model for taking into account gate resistance induced propagation delay | Physics | 7 | Expired |
| US5712200A | N-well resistor as a ballast resistor for output MOSFET | Electricity | 6 | Expired |
| US5714785A | Asymmetric drain/source layout for robust electrostatic discharge protection | Electricity | 4 | Expired |
| US6660579B1 | Zero power memory cell with improved data retention | Electricity | 3 | Expired |
| US11246444B2 | Punching-free mounting assembly for installing a curtain | Fixed Constructions | 2 | Active |
| USD1051638S1 | Top beam for curtain | General | 2 | Active |
| US6689697B1 | Method of forming uniformly planarized structure in a semiconductor wafer | Electricity | 2 | Expired |
| USD929349S1 | Curtain controller | General | 2 | Active |
| USD1045794S1 | Curtain motor | General | 2 | Active |
| US6099576A | System for designing and manufacturing CMOS inverters by estimating gate RC delay | Physics | 2 | Expired |
| US6545313B1 | EEPROM tunnel window for program injection via P+ contacted inversion | Electricity | 2 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.