Method of forming single bitline contact using line shape masks for vertical transistors in DRAM/e-DRAM devices

US6660581B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Haining Yang · Wappingers Falls, US
• Ramachandra Divakaruni · Ossining, US

Key dates

• Filing date: Mar 11, 2003
• Grant date: Dec 9, 2003
• Expiry date: Mar 11, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/047

Abstract

Form a bitline contact to deep trench gates separated from a substrate body by gate oxide with sources next to the gates near the top of the body and drains formed in the body of the substrate connected to a deep trench capacitor, with sidewall spacers between the gates and upper sidewalls of the deep trench. Form a patterning mask over the device exposing a portion of an upper surface of a gate electrode at the top surface of the substrate with a patterning mask patterned by a line shaping master mask. Etch a divot reaching down into the gate electrode alongside a deep trench sidewall spacer juxtaposed with a source. Fill the divot with a dielectric material. Form a wordline stack with a wordline and a silicon nitride cap in contact with the gate electrode. Form an etch resistant conformal liner and then form a planarized ILD layer and a glass layer covering the ILD layer. Form a bitline contact mask patterned by the line shaping master mask, with a bitline contact therethrough above the source region juxtaposed with the deep trench sidewall spacer. Etch a via hole down to the source region in the pattern of the bitline contact mask and form a bitline contact.