Haining Yang
277Patents
24h-index
142Co-inventors
93Inventor score
Filing activity: Jan 20, 1998 → Apr 30, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7625790B2 | FinFET with sublithographic fin width | Electricity | 114 | Active |
| US6891192B2 | Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions | Electricity | 114 | Expired |
| US7791109B2 | Metal silicide alloy local interconnect | Emerging Cross-Sectional Technologies | 108 | Active |
| US6881635B1 | Strained silicon NMOS devices with embedded source/drain | Electricity | 102 | Expired |
| US7553760B2 | Sub-lithographic nano interconnect structures, and method for forming same | Electricity | 101 | Active |
| US7816231B2 | Device structures including backside contacts, and methods for forming same | Electricity | 99 | Active |
| US6524867B2 | Method for forming platinum-rhodium stack as an oxygen barrier | Electricity | 88 | Expired |
| US7605081B2 | Sub-lithographic feature patterning using self-aligned self-assembly polymers | Electricity | 87 | Active |
| US7592247B2 | Sub-lithographic local interconnects, and methods for forming same | Electricity | 71 | Active |
| US7557424B2 | Reversible electric fuse and antifuse structures for semiconductor devices | Electricity | 67 | Active |
| US7767099B2 | Sub-lithographic interconnect patterning using self-assembling polymers | Emerging Cross-Sectional Technologies | 67 | Active |
| US7514339B2 | Method for fabricating shallow trench isolation structures using diblock copolymer patterning | Electricity | 56 | Active |
| US8083958B2 | Patterning method using a combination of photolithography and copolymer self-assemblying lithography techniques | Emerging Cross-Sectional Technologies | 56 | Active |
| US6518610B2 | Rhodium-rich oxygen barriers | Electricity | 53 | Expired |
| US6939814B2 | Increasing carrier mobility in NFET and PFET transistors on a common wafer | Electricity | 51 | Expired |
| US6946709B2 | Complementary transistors having different source and drain extension spacing controlled by different spacer sizes | Electricity | 34 | Expired |
| US7781847B2 | Device patterned with sub-lithographic features with variable widths | Emerging Cross-Sectional Technologies | 33 | Active |
| US7984408B2 | Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering | Electricity | 31 | Active |
| US6906360B2 | Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions | Electricity | 30 | Expired |
| US7867832B2 | Electrical fuse and method of making | Electricity | 29 | Active |
| US7098536B2 | Structure for strained channel field effect transistor pair having a member and a contact via | Electricity | 27 | Expired |
| US7002209B2 | MOSFET structure with high mechanical stress in the channel | Electricity | 26 | Expired |
| US7737501B2 | FinFET SRAM with asymmetric gate and method of manufacture thereof | Electricity | 25 | Active |
| US7193254B2 | Structure and method of applying stresses to PFET and NFET transistor channels for improved performance | Electricity | 25 | Expired |
| US6660581B1 | Method of forming single bitline contact using line shape masks for vertical transistors in DRAM/e-DRAM devices | Electricity | 23 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.