Method for fabricating heterojunction bipolar transistors
US6660607B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Mar 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/021
Abstract
A method for fabricating a heterojunction bipolar transistor having collector, base and emitter regions is disclosed. In an exemplary embodiment of the invention, the method includes forming a silicon epitaxial layer upon a substrate, the silicon epitaxial layer defining the collector region. An oxide stack is formed upon the silicon epitaxial layer and a nitride layer is then formed upon the oxide stack. Next, an emitter opening is defined within the nitride layer before a base cavity is formed within the oxide stack. The base cavity extends laterally beyond the width of the emitter opening. A silicon-germanium epitaxial layer is grown within the base cavity, the silicon-germanium epitaxial layer defining the base region. Finally, a polysilicon layer is deposited upon said silicon-germanium epitaxial layer, the polysilicon layer defining the emitter region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.