Interconnect structure and method of making same
US6660945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2001 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Nov 23, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.