MOSFET driver matching circuit for an enhancement mode JFET
US6661276B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Jul 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/04123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A matching circuit for coupling a conventional metal-oxide semiconductor field effect transistor (MOSFET) driver to the gate of a junction field effect transistor (JFET). A driver circuit optimized for driving a MOSFET is combined with a matching circuit to provide gate drive for a JFET. The matching circuit comprises a resistor and capacitor in parallel. For driving enhancement mode JFETs having a gate grid array structure and a pinch-off voltage greater than 0.4 volts, the range of resistor values is 10 to 200 ohms, and the range of capacitor values is 1 to 100 nF. For devices having a pinch-off voltage less than 0.4 volts, the range of resistor values is 100 to 2000 ohms. The matching circuit may further include a diode to provide a bias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.