Three-transistor DRAM cell and associated fabrication method

US6661701B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Claus Dahl · Dresden, DE
• Siegmar Koppe · Laatzen, DE

Key dates

• Filing date: May 30, 2002
• Grant date: Dec 9, 2003
• Expiry date: May 30, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/00

Abstract

The three-transistor DRAM cell has a memory transistor formed as a field-effect transistor with a short-channel section and a long-channel section. A second insulating layer and a conductive layer are additionally formed on a gate layer of the memory transistor. A substantially constant voltage value is present between a potential of the conductive layer and a potential of the substrate area. A three-transistor DRAM cell with improved interference immunity and charge retention time