Implementation of an inhibit during soft programming to tighten an erase voltage distribution
US6661711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2002 |
| Grant date | Dec 9, 2003 |
| Priority date | — |
| Expiry date | Feb 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for tightening an erased bit threshold voltage distribution are disclosed. According to one aspect of the present invention, a method for processing erased bits associated with an erased bit distribution which includes an over-erased bit which has a first value that is less than a first threshold voltage value and a bit that has a second value that substantially exceeds a second threshold voltage value includes inhibiting the fast bit. The method also includes applying a soft program pulse to the erased bits such that inhibiting the fast bit substantially prevents the second value from changing and applying the soft program pulse to the over-erased bit substantially causes the first value to increase. In one embodiment, applying the soft program pulse to the over-erased bit substantially causes the first value to increase to a value that is greater than or equal to the first threshold voltage value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.